Angger Baskoro, Onny Setyawati, Ponco Siwindarto, Chua-Chin Wang
This investigation presents an 8-bit shift register based on a lower-power double-edge triggered (DETFF) flip-flop. The 8-bit shift register based on the low-power DETFF is carried out by using Cadence Virtuoso version 5.1 and TSMC 0.18 µm CMOS technology. The major contribution of the proposed design is a method using a double-clocking technique to latch data bits such that shorter time delay and the less power dissipation are achieved at the same time. The all-PVT-corner (process, voltage, temperature) post-layout simulation results demonstrates 34.970 mW at the highest 125 MHz clock rate. © Proceedings of 2018 the 8th International Workshop on Computer Science and Engineering, WCSE 2018. All rights reserved.
National Sun Yat-Sen University, University of Brawijaya, China
