Agung Setiabudi, Hiroki Tamura, Koichi Tanno, Zainul Abidin
One of the most important building blocks in analog to digital converter (ADC) is sample and hold (S/H) circuit. The function of this circuit is to hold the input voltage until ADC completes the conversion process. The accuracy of S/H circuit is limited by channel charge injection and clock feedthrough. In this paper, a new method to minimize hold error in CMOS TG switch S/H circuit using feedforward neural network as function approximation is proposed. The basic idea of the proposed method is to minimize hold error by adjusting the width of NMOS transistor (Wn) and PMOS transistor (Wp) in CMOS switch numerically using a trained neural network. The performance of the proposed method is evaluated using HSPICE with 180 nm CMOS standard process. As a result, HSPICE simulation verified that hold error produced by S/H circuit whose Wp and Wn are generated using the minimization method is mostly zero. The maximum and average hold error is 20 μ V and 2 μ V, respectively. © 2018 IEEE.
Dept. of Materials and Informatics, University of Miyazaki, Miyazaki, Japan; Dept. of Environmental, Robotics University of Miyazaki, Miyazaki, Japan; Dept. of Electrical and System, University of Miyazaki, Miyazaki, Japan; Dept. of Electrical Engineering, Brawijaya University, Malang, Indonesia
